The present invention relates to semiconductor fabrication, and in particular to semiconductor devices with composite etch stop layers and related fabrication methods.
Large, advanced semiconductor integrated circuits typically contain a large number of metallization levels to allow for the complex electrical interconnects required for the millions of semiconductor devices included in such integrated circuits.
The reduction in size of such integrated circuits has resulted in levels of electrically conductive interconnects being placed closer together vertically, as well as horizontally. As a result, capacitance has increased between such conductive portions, resulting in loss of speed and increased cross-talk. One proposed approach to solve this problem of high capacitance is to replace the conventional silicon oxide (SiO2) dielectric material used in the damascene wiring technology with another insulation material having a lower dielectric constant to thereby lower the capacitance.
Normally, a silicon nitride layer is often used in an integrated circuit structure as an etch stop layer. However, problems such as via poisoning, resist scumming and via blinding can occur in the integrated circuit structure utilizing a dielectric layer. For example, in an integrated circuit structure using a low-k dielectric layer and nitrogen-containing silicon nitride etch stop layer, such problems can occur due to outgassing. Also, a single etch stop layer may provide insufficient etching selectivity relative to a dielectric layer formed thereon. Thus, undesired breakthrough might happen that can damage the integrated circuit structure.